A novel hot carrier reliability monitor for LDD p-MOSFETs

Abstract

The gate-edge shape of an LDD p-MOSFET exhibits large influences upon the hot carrier induced degradation and its performances. It is observed that the gate-to-drain tunneling current is strongly correlated to the reentrant gate oxide thickness and to the device degradation. A simple model is then constructed to provide an explanation for the observation. Under the tunneling current measurement conditions, a thicker oxide at the gate-edge leads to a weaker peak electric field in the p-LDD and to a lower gate-to-drain current. On the other hand, under the hot carrier stressing conditions, the thicker oxide decreases the oxide electric field and thus suppresses the hot electron injection. The observed correlation can be employed to monitor the process induced gate-edge (overlap) variation.