Please use this identifier to cite or link to this item: https://doi.org/10.1109/TCSII.2013.2258270
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dc.titleA new system architecture for future long-term high-density neural recording
dc.contributor.authorXu, J.
dc.contributor.authorWu, T.
dc.contributor.authorYang, Z.
dc.date.accessioned2014-06-16T09:32:17Z
dc.date.available2014-06-16T09:32:17Z
dc.date.issued2013
dc.identifier.citationXu, J., Wu, T., Yang, Z. (2013). A new system architecture for future long-term high-density neural recording. IEEE Transactions on Circuits and Systems II: Express Briefs 60 (7) : 403-406. ScholarBank@NUS Repository. https://doi.org/10.1109/TCSII.2013.2258270
dc.identifier.issn15497747
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/54547
dc.description.abstractThis brief presents a new system architecture for neural recording to allow higher recording density and more tolerance to interface degeneration and artifacts. Compared with its conventional counterpart, the proposed architecture has a frequency-dependent gain stage that inherently rejects dc offset and attenuates low-frequency interferences. In the digital domain, frequency compensation is used to restore the signals 'seen' by an electrode. Powered by a switched-capacitor design, the proposed architecture can lead to major improvements on system performance metrics, including input impedance, distortion, and dynamic range. In simulations with different electrode sizes and degeneration levels, the proposed architecture consistently gives high-fidelity recording data. We argue that the proposed architecture is more suitable for long-term high-density invasive brain-computer interface experiments as a replacement to better support a mimicked 'Moore's Law' on recording density. © 2004-2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TCSII.2013.2258270
dc.sourceScopus
dc.subjectDynamic range (DR)
dc.subjectfrequency shaping
dc.subjectinput impedance
dc.subjectneural recording
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TCSII.2013.2258270
dc.description.sourcetitleIEEE Transactions on Circuits and Systems II: Express Briefs
dc.description.volume60
dc.description.issue7
dc.description.page403-406
dc.identifier.isiut000322030600007
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