A FSLE-based transceiver for combined synchronization and equalization in partial response systems

Abstract

This paper presents a new technique for combined equalization and synchronization in a partial response communication system. Using just a single FSLE (Fractionally-Spaced Linear Equalizer) structure, the work of synchronization and equalization is performed concurrently using an improved LMS (least mean square) firmware algorithm which incorporates a new timing error detection method known as SC-PMC (self-convoluting partial mass center). Since the SC-PMC technique incorporates synchronization as well, the usual synchronization block for partial response signal synchronization is no longer necessary. This will clearly result in a significant reduction in transceiver components. Software simulation of the new technique as well as firmware implementation on two TI C6711 DSP cards will demonstrate the usefulness of the contribution. This work, although reported for a communication application, is also applicable in HDD (hard disk drive) applications where partial response techniques are often employed for HDD read back functionalities.