Please use this identifier to cite or link to this item:
https://doi.org/10.1109/16.662798
DC Field | Value | |
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dc.title | A comparison of hot-carrier degradation in tungsten polycide gate and poly gate p-MOSFETs | |
dc.contributor.author | Ang, D.S. | |
dc.contributor.author | Ling, C.H. | |
dc.date.accessioned | 2014-06-16T09:24:59Z | |
dc.date.available | 2014-06-16T09:24:59Z | |
dc.date.issued | 1998 | |
dc.identifier.citation | Ang, D.S., Ling, C.H. (1998). A comparison of hot-carrier degradation in tungsten polycide gate and poly gate p-MOSFETs. IEEE Transactions on Electron Devices 45 (4) : 895-903. ScholarBank@NUS Repository. https://doi.org/10.1109/16.662798 | |
dc.identifier.issn | 00189383 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/53991 | |
dc.description.abstract | A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n/sup +/ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi/sub x/ p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C/sub gd//sup s/ measurement shows increased susceptibility to electron trapping in the WSi/sub x/ device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on /spl Delta/V/sub t/=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 /spl mu/m, the reduced hot-carrier lifetime of WSi/sub x/ p-MOSFETs suggests that WF/sub 6/-based silicidation may not be appropriate for deep submicrometer CMOS devices. © 1963-2012 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/16.662798 | |
dc.source | Scopus | |
dc.type | Article | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.contributor.department | BACHELOR OF TECHNOLOGY PROGRAMME | |
dc.description.doi | 10.1109/16.662798 | |
dc.description.sourcetitle | IEEE Transactions on Electron Devices | |
dc.description.volume | 45 | |
dc.description.issue | 4 | |
dc.description.page | 895-903 | |
dc.description.coden | IETDA | |
dc.identifier.isiut | 000072662800021 | |
Appears in Collections: | Staff Publications |
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