Please use this identifier to cite or link to this item: https://doi.org/10.1109/JSSC.2008.923616
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dc.titleA CMOS readout circuit for SOI resonant accelerometer with 4-μg bias stability and 20-μg/√Hz resolution
dc.contributor.authorHe, L.
dc.contributor.authorXu, Y.P.
dc.contributor.authorPalaniapan, M.
dc.date.accessioned2014-06-16T09:24:12Z
dc.date.available2014-06-16T09:24:12Z
dc.date.issued2008-06
dc.identifier.citationHe, L., Xu, Y.P., Palaniapan, M. (2008-06). A CMOS readout circuit for SOI resonant accelerometer with 4-μg bias stability and 20-μg/√Hz resolution. IEEE Journal of Solid-State Circuits 43 (6) : 1480-1490. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2008.923616
dc.identifier.issn00189200
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/53943
dc.description.abstractA fully differential CMOS readout circuit for SOI resonant accelerometer is reported. The readout circuit is essentially an oscillator, consisting of an oscillator and a low noise automatic amplitude control (AAC) loop. A differential sense resonator is proposed to facilitate fully differential circuit topology and improves the SNR under a 3.3-V supply. A second-order AAC loop filter and a novel chopper stabilized rectifier are employed in the AAC loop to remove the noises, in particular, the 1/f noise, and to minimize the phase noise caused by the amplitude stiffening effect. The strong driving feedthrough is avoided by separating the drive and sense operation in the time domain, while using the same electrodes. The complete resonant accelerometer operates under a 3.3-V supply and achieves 140-Hz/g scaling factor, 20 μg/√Hz resolution and 4 μg bias stability. The readout circuit draws 7 mA under 3.3-V supply. © 2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/JSSC.2008.923616
dc.sourceScopus
dc.subjectAccelerometer
dc.subjectBias stability
dc.subjectMEMS resonator
dc.subjectOscillator
dc.subjectPhase noise
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/JSSC.2008.923616
dc.description.sourcetitleIEEE Journal of Solid-State Circuits
dc.description.volume43
dc.description.issue6
dc.description.page1480-1490
dc.description.codenIJSCB
dc.identifier.isiut000256310000015
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