Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/50636
DC FieldValue
dc.titleOn-chip compensation of dark current in infrared focal plane arrays
dc.contributor.authorNg, M.W.
dc.contributor.authorChee, Y.H.
dc.contributor.authorXu, Y.P.
dc.contributor.authorKarunasiri, G.
dc.date.accessioned2014-04-23T03:02:01Z
dc.date.available2014-04-23T03:02:01Z
dc.date.issued2001
dc.identifier.citationNg, M.W.,Chee, Y.H.,Xu, Y.P.,Karunasiri, G. (2001). On-chip compensation of dark current in infrared focal plane arrays. Proceedings - IEEE International Symposium on Circuits and Systems 3 : 509-512. ScholarBank@NUS Repository.
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/50636
dc.description.abstractA readout technique for infrared (IR) focal plane arrays (FPAs), involving on-chip compensation of leakage current is presented. This technique employs a tuneable compensation circuit, controlled by a voltage-to-current converter to eliminate the bulk of the leakage current prior to the integration of the weak photo signal at pixel level. To further improve the performance, a correlated double sampling (CDS) circuit is incorporated at the column level to eliminate the fixed pattern noise (FPN) inherent in large sensor arrays with multiple readout lines. A 32×29 element FPA with CMOS sensors was fabricated using 0.8-μm CMOS technology for testing the concept. To mimic the large leakage associated with IR detectors, the testing was carried out under an external light illumination. The results show good compensation of the current caused by the external light and this indicates the effectiveness of the scheme.
dc.sourceScopus
dc.subjectCompensation circuit
dc.subjectCorrelated double sampling
dc.subjectDark current
dc.subjectFixed pattern noise
dc.subjectFocal plane arrays
dc.subjectInfrared imagers
dc.subjectReadout electronics
dc.typeConference Paper
dc.contributor.departmentELECTRICAL ENGINEERING
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.volume3
dc.description.page509-512
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

Show simple item record
Files in This Item:
There are no files associated with this item.

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.