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|Title:||An integrated performance and power model for superscalar processor designs||Authors:||Zhu, Y.
|Issue Date:||2005||Citation:||Zhu, Y.,Wong, W.-F.,Andrei, S. (2005). An integrated performance and power model for superscalar processor designs. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2 : 948-951. ScholarBank@NUS Repository.||Abstract:||On current superscalar processors, performance and power issues cannot be decoupled for designers. Extensive simulations are usually required to meet both power and performance constraints. This paper describes an integrated performance and power analytical model. The model's performance and power results are in good agreement with detailed simulations, previous models and physically measured results. For designers, the model enables quick and flexible explorations into a subset of even entire huge parameter space of more than 15 workload and architectural parameters plus leakage power, feature sizes, clock and voltage. © 2005 IEEE.||Source Title:||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC||URI:||http://scholarbank.nus.edu.sg/handle/10635/43270||ISBN:||0780387368|
|Appears in Collections:||Staff Publications|
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