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|Title:||A retargetable software timing analyzer using architecture description language||Authors:||Li, X.
|Issue Date:||2007||Citation:||Li, X.,Roychoudhury, A.,Mitra, T.,Mishra, P.,Cheng, X. (2007). A retargetable software timing analyzer using architecture description language. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC : 396-401. ScholarBank@NUS Repository. https://doi.org/10.1109/ASPDAC.2007.358018||Abstract:||Worst Case Execution Time (WCET) is an essential input for performance and schedulability analysis of real-time systems. Static WCET analysis requires program path analysis and microar-chitecture modeling. Despite almost two decades of research, WCET analysis has not enjoyed wide acceptance in industry. This is in part due to the difficulty in microarchitecture modeling of modern processors. Given the large number of embedded processors available in the market, retargetability of the WCET analysis framework is a serious issue. In this paper, we address it using Architecture Description Language (ADL). Starting with the ADL of a target processor, the proposed framework automatically generates graph-based execution models to capture timing effects of instructions in the pipeline. This pipeline model coupled with parameterized models of cache and branch prediction lead to a WCET framework that is safe, accurate and retargetable. © 2007 IEEE.||Source Title:||Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC||URI:||http://scholarbank.nus.edu.sg/handle/10635/41806||ISBN:||1424406293||DOI:||10.1109/ASPDAC.2007.358018|
|Appears in Collections:||Staff Publications|
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