Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/41602
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dc.titleSatisfying real-time constraints with custom instructions
dc.contributor.authorYu, P.
dc.contributor.authorMitra, T.
dc.date.accessioned2013-07-04T08:31:22Z
dc.date.available2013-07-04T08:31:22Z
dc.date.issued2005
dc.identifier.citationYu, P., Mitra, T. (2005). Satisfying real-time constraints with custom instructions. CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis : 166-171. ScholarBank@NUS Repository.
dc.identifier.isbn1595931619
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/41602
dc.description.abstractInstruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average). Copyright 2005 ACM.
dc.sourceScopus
dc.subjectCustomizable processors
dc.subjectInstruction-set extensions
dc.subjectReal-time systems
dc.subjectWorst-case execution time
dc.typeConference Paper
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.sourcetitleCODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis
dc.description.page166-171
dc.identifier.isiutNOT_IN_WOS
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