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|Title:||A reconfigurable instruction memory hierarchy for embedded systems||Authors:||Ge, Z.
|Issue Date:||2005||Citation:||Ge, Z.,Lim, H.B.,Wong, W.F. (2005). A reconfigurable instruction memory hierarchy for embedded systems. Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL 2005 : 7-12. ScholarBank@NUS Repository. https://doi.org/10.1109/FPL.2005.1515691||Abstract:||The performance of the instruction memory hierarchy is of crucial importance in embedded systems. In this paper, we propose a reconfigurable instruction memory hierarchy for embedded systems whose architectural parameters can be customized for specific applications. The proposed instruction memory hierarchy consists of an instruction cache and a scratchpad memory (SPM). We propose an algorithm to manage this instruction memory hierarchy and optimize its performance. Given a fixed amount of reconfigurable on-chip storage resources and an application, our algorithm determines the sizes of the SPM and the instruction cache to best suit the application. It analyzes the application, partitions the available storage resources into SPM and cache, and assigns instructions to them. Our algorithm aims to reduce the instruction fetch miss rate, improve the system performance, and reduce the energy consumption. We have implemented this reconfigurable instruction memory hierarchy on the Altera Nios II FPGA platform. Our experimental results using five benchmarks from the MediaBench and the MiBench suites show that our proposed architecture provides significant performance improvements and energy reduction. © 2005 IEEE.||Source Title:||Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL||URI:||http://scholarbank.nus.edu.sg/handle/10635/41248||ISBN:||0780393627||DOI:||10.1109/FPL.2005.1515691|
|Appears in Collections:||Staff Publications|
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