Please use this identifier to cite or link to this item: https://doi.org/10.1145/1950413.1950459
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dc.titleCo-synthesis of FPGA-based application-specific floating point SIMD accelerators
dc.contributor.authorHagiescu, A.
dc.contributor.authorWong, W.-F.
dc.date.accessioned2013-07-04T08:22:48Z
dc.date.available2013-07-04T08:22:48Z
dc.date.issued2011
dc.identifier.citationHagiescu, A.,Wong, W.-F. (2011). Co-synthesis of FPGA-based application-specific floating point SIMD accelerators. ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA : 247-256. ScholarBank@NUS Repository. <a href="https://doi.org/10.1145/1950413.1950459" target="_blank">https://doi.org/10.1145/1950413.1950459</a>
dc.identifier.isbn9781450305549
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/41237
dc.description.abstractThe constant push for feature richness in mobile and embedded devices has significantly increased computational demand. However, stringent energy constraints typically remain in place. Embedding processor cores in FPGAs offers a path to having customized instruction processors that can meet the performance and energy demands. Ideally, the customization process should be automated to reduce the design effort, and indirectly the time to market. However, the automatic generation of custom extensions for floating point computation remains a challenge in FPGA co-design. We propose an approach for accelerating such computation via application-specific SIMD extensions. We describe an automated co-design toolchain that generates code and application-specific platform extensions that implement SIMD instructions with a parameterizable number of vector elements. The parallelism exposed by encapsulating computation in vector instructions is matched to an adjustable pool of execution units. Experiments on actual hardware show significant performance improvements. Our framework provides an important extension to the capabilities of embedded processor FPGAs which traditionally dealt with bit, integer, and low intensity floating point code, to now being able to handle vectorizable floating point computation. Copyright 2011 ACM.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1145/1950413.1950459
dc.sourceScopus
dc.subjectCo-synthesis
dc.subjectCustom instructions
dc.subjectSIMD
dc.typeConference Paper
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.doi10.1145/1950413.1950459
dc.description.sourcetitleACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA
dc.description.page247-256
dc.identifier.isiutNOT_IN_WOS
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