Adaptive compiler directed prefetching for EPIC processors

Abstract

The widely acknowledged performance gap between processors and memory has been the subject of much research. In the Explicitly Parallel Instruction Computing (EPIC) paradigm, the combination of in-order issue and the presence of a large number of parallel functional units exacerbate the problem. Prefetching, by hardware, software, or a combination of both, is one of the primary mechanisms advocated to alleviate this problem. In this paper, we propose a new mechanism readily suitable for implementation in EPIC processors. Specifically, we introduce a predicated prefetch operation which leverages the concept of an informing load to dynamically adapt to run-time memory behaviors. Furthermore, we employ predicated Prefetching in a new optimization framework, which also consists of data remapping and off-line learning of Markovian predictors. This distinguishes our approach from early software Prefetching techniques that only involve static program analysis. Our experiments show that the proposed framework can effectively remove 10%-30% of the stall cycles due to cache misses for benchmarks from the well-known SPEC and OLDEN suites.