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|Title:||Intruction cache locking using temporal reuse profile||Authors:||Liang, Y.
Temporal reuse profile
|Issue Date:||2010||Citation:||Liang, Y.,Mitra, T. (2010). Intruction cache locking using temporal reuse profile. Proceedings - Design Automation Conference : 344-349. ScholarBank@NUS Repository. https://doi.org/10.1145/1837274.1837362||Abstract:||The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the performance of an application. Modern embedded processors often feature cache locking mechanisms that allow memory blocks to be locked in the cache under software control. Cache locking was primarily designed to offer timing predictability for hard real-time applications. Hence, the compiler optimization techniques focus on employing cache locking to improve worst-case execution time. However, cache locking can be quite effective in improving the average-case execution time of general embedded applications as well. In this paper, we explore static instruction cache locking to improve average-case program performance. We introduce temporal reuse profile to accurately and efficiently model the cost and benefit of locking memory blocks in the cache. We propose an optimal algorithm and a heuristic approach that use the temporal reuse profile to determine the most beneficial memory blocks to be locked in the cache. Experimental results show that locking heuristic achieves close to optimal results and can improve the cache miss rate by up to 24% across a suite of real-world benchmarks. Moreover, our heuristic provides significant improvement compared to the state-of-the-art locking algorithm both in terms of performance and efficiency. Copyright 2010 ACM.||Source Title:||Proceedings - Design Automation Conference||URI:||http://scholarbank.nus.edu.sg/handle/10635/40366||ISBN:||9781450300025||ISSN:||0738100X||DOI:||10.1145/1837274.1837362|
|Appears in Collections:||Staff Publications|
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