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dc.titleRealizing live sequence charts in SystemVerilog
dc.contributor.authorWang, H.H.
dc.contributor.authorSun, J.
dc.contributor.authorQin, S.
dc.contributor.authorDong, J.S.
dc.identifier.citationWang, H.H.,Sun, J.,Qin, S.,Dong, J.S. (2007). Realizing live sequence charts in SystemVerilog. First Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering, TASE '07 : 379-388. ScholarBank@NUS Repository. <a href="" target="_blank"></a>
dc.description.abstractThe design of an embedded control system starts with an investigation of properties and behaviors of the process evolving within its environment, and an analysis of the requirement for its safety performance. In early stages, system requirements are often specified as scenarios of behavior using sequence charts for different use cases. This specification must be precise, intuitive and expressive enough to capture different aspects of embedded control systems. As a rather rich and useful extension to the classical message sequence charts, Live Sequence Charts (LSC), which provide a rich collection of constructs for specifying both possible and mandatory behaviors, are very suitable for designing an embedded control system. However, it is not a trivial task to realize a high-level design model in executable program codes effectively and correctly. This paper tackles the challenging task by providing a mapping algorithm to automatically synthesize SystemVerilog programs from given LSC specifications. © 2007 IEEE.
dc.typeConference Paper
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.sourcetitleFirst Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering, TASE '07
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