Please use this identifier to cite or link to this item: https://doi.org/10.1007/s10703-007-0041-6
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dc.titleMemory model sensitive bytecode verification
dc.contributor.authorHuynh, T.Q.
dc.contributor.authorRoychoudhury, A.
dc.date.accessioned2013-07-04T07:50:31Z
dc.date.available2013-07-04T07:50:31Z
dc.date.issued2007
dc.identifier.citationHuynh, T.Q., Roychoudhury, A. (2007). Memory model sensitive bytecode verification. Formal Methods in System Design 31 (3) : 281-305. ScholarBank@NUS Repository. https://doi.org/10.1007/s10703-007-0041-6
dc.identifier.issn09259856
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/39828
dc.description.abstractModern concurrent programming languages like C# and Java have a programming language level memory model, which captures the set of all allowed behaviors of programs on any implementation platform-uni- or multi-processor. Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a program thread. Therefore, programs verified correct by assuming Sequential Consistency (that is, each thread proceeds in program order) may not behave correctly on certain platforms! One solution to this problem is to develop program checkers which are memory model sensitive. In this paper, we develop a bytecode level invariant checker for the programming language C#. Our checker identifies program states which are reached only because the C# memory model is more relaxed than Sequential Consistency. It employs partial order reduction strategies to speed up the search. These strategies are different from standard partial order reduction methods since our search also considers execution traces containing bytecode re-orderings. Furthermore, our checker identifies (a) operation re-orderings which cause undesirable states to be reached, and (b) simple program modifications-by inserting memory barrier operations-which prevent such undesirable re-orderings. © 2007 Springer Science+Business Media, LLC.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1007/s10703-007-0041-6
dc.sourceScopus
dc.subjectBytecode verification
dc.subjectProgramming language memory models
dc.subjectSoftware model checking
dc.typeArticle
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.doi10.1007/s10703-007-0041-6
dc.description.sourcetitleFormal Methods in System Design
dc.description.volume31
dc.description.issue3
dc.description.page281-305
dc.description.codenFMSDE
dc.identifier.isiut000250580800005
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