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Title: Computer-aided dispatch system family architecture and verification: An integrated formal approach
Authors: Sun, J.
Dong, J.S. 
Jarzabek, S. 
Wang, H.
Issue Date: 2006
Citation: Sun, J., Dong, J.S., Jarzabek, S., Wang, H. (2006). Computer-aided dispatch system family architecture and verification: An integrated formal approach. IEE Proceedings: Software 153 (3) : 102-112. ScholarBank@NUS Repository.
Abstract: Software architecture is an important level of description for software systems. Formal modelling techniques can be used to define and verify software architectures precisely. An integrated formal approach to the architecture modelling and verification of a computer-aided dispatch (CAD) system family, is presented. An incremental three-layer model, that is, architecture style layer, generic system layer and customised system layer, is presented to capture the design of the CAD system family. Critical CAD system properties in the architecture models are formally verified by using the state and event-based proof techniques of the underlying specification language. In summary, it is demonstrated that integrated formal techniques could be a good candidate for modelling and verifying various levels of descriptions of software architectures.
Source Title: IEE Proceedings: Software
ISSN: 14625970
DOI: 10.1049/ip-sen:20050014
Appears in Collections:Staff Publications

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