Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/35266
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dc.titlePlanar microspring integrated circuit chip interconnection to next level
dc.contributorNATIONAL UNIVERSITY OF SINGAPORE
dc.contributorAGENCY FOR SCIENCE, TECHNOLOGY & RESEARCH
dc.contributorGEORGIA TECH RESEARCH CORPORATION
dc.contributor.authorTAY, ANDREW AH ONG
dc.contributor.authorANG, SIMON SAW-TEONG
dc.contributor.authorLIAO, EBIN
dc.date.accessioned2012-11-01T05:58:10Z
dc.date.available2012-11-01T05:58:10Z
dc.date.issued2006-09-07
dc.identifier.citationTAY, ANDREW AH ONG,ANG, SIMON SAW-TEONG,LIAO, EBIN (2006-09-07). Planar microspring integrated circuit chip interconnection to next level. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/35266
dc.description.abstractAn interconnect structure for interconnecting an integrated circuit (IC) chip to a next level, a method of fabricating the interconnect at wafer level, and a method of interconnecting an integrated circuit (IC) chip to the next level. The interconnect structure comprises one or more planar micro-spring elements formed on a packaging surface of the chip and connected to an interconnection pad; wherein the interconnection pad is resiliently moveable horizontally and vertically with respect to the surface of the chip. A layer of solder is preferably electroplated onto the interconnection pad to provide interconnection to the next level. In a variation of the interconnect structure, a metal column is fabricated onto the interconnection pad prior to electroplating the solder layer.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US20060197232A1
dc.sourcePatSnap
dc.typePatent
dc.contributor.departmentMECHANICAL ENGINEERING
dc.identifier.isiutNOT_IN_WOS
dc.description.patentnoUS20060197232A1
dc.description.patenttypePublished Application
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