Method and apparatus for a digital clock multiplication circuit

Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/34916

DC Field	Value
dc.title	Method and apparatus for a digital clock multiplication circuit
dc.contributor	THE NATIONAL UNIVERSITY OF SINGAPORE
dc.contributor.author	LYE, KIN MUN
dc.contributor.author	JOE, JURIANTO
dc.date.accessioned	2012-10-08T08:22:39Z
dc.date.available	2012-10-08T08:22:39Z
dc.date.issued	2003-01-09
dc.identifier.citation	LYE, KIN MUN,JOE, JURIANTO (2003-01-09). Method and apparatus for a digital clock multiplication circuit. ScholarBank@NUS Repository.
dc.identifier.uri	http://scholarbank.nus.edu.sg/handle/10635/34916
dc.description.abstract	A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.
dc.description.uri	http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US20030006850A1
dc.source	PatSnap
dc.type	Patent
dc.contributor.department	ELECTRICAL & COMPUTER ENGINEERING
dc.identifier.isiut	NOT_IN_WOS
dc.description.patentno	US20030006850A1
dc.description.patenttype	Published Application
Appears in Collections:	Staff Publications

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