Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/32637
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dc.titleProcess for device using partial SOI
dc.contributor.authorJUN, CAI
dc.contributor.authorHONG, REN CHANG
dc.contributor.authorNAGARAJAN, RANGANATHAN
dc.contributor.authorBALASUBRAMANIAN, NARAYANAN
dc.contributor.authorLIANG, YUNG CHII
dc.date.accessioned2012-05-02T02:28:08Z
dc.date.available2012-05-02T02:28:08Z
dc.date.issued2003-04-22
dc.identifier.citationJUN, CAI,HONG, REN CHANG,NAGARAJAN, RANGANATHAN,BALASUBRAMANIAN, NARAYANAN,LIANG, YUNG CHII (2003-04-22). Process for device using partial SOI. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/32637
dc.description.abstractA process for manufacturing a buried oxide layer for use in partial SOI structures is described. The process begins with the etching of deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pinch-off occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of wade whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS structure is also described together with performance data for the resulting device.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US6551937
dc.sourcePatSnap
dc.typePatent
dc.contributor.departmentMATERIALS SCIENCE
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.identifier.isiutNOT_IN_WOS
dc.description.patentnoUS6551937
dc.description.patenttypeGranted Patent
dc.contributor.patentassigneeINSTITUTE OF MICROELECTRONICS (SINGAPORE, SG)
dc.contributor.patentassigneeNATIONAL UNIVERSITY OF SINGAPORE
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