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https://scholarbank.nus.edu.sg/handle/10635/32579
DC Field | Value | |
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dc.title | Passivation of copper interconnect surfaces with a passivating metal layer | |
dc.contributor.author | CHAN, LAP | |
dc.contributor.author | YAP, KUAN PEI | |
dc.contributor.author | TEE, KHENG CHOK | |
dc.contributor.author | IP, FLORA S. | |
dc.contributor.author | LOH, WYE BOON | |
dc.date.accessioned | 2012-05-02T02:27:19Z | |
dc.date.available | 2012-05-02T02:27:19Z | |
dc.date.issued | 2000-08-08 | |
dc.identifier.citation | CHAN, LAP,YAP, KUAN PEI,TEE, KHENG CHOK,IP, FLORA S.,LOH, WYE BOON (2000-08-08). Passivation of copper interconnect surfaces with a passivating metal layer. ScholarBank@NUS Repository. | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/32579 | |
dc.description.abstract | An interconnect line on an IMD layer on a semiconductor device is formed in an interconnect hole in the IMD layer. The interconnect hole has walls and a bottom in the IMD layer. A diffusion barrier is formed on the walls and the bottom of the hole. Fill the interconnect hole with a copper metal line. Perform a CMP step to planarize the device and to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole. Alternatively, a blanket deposit of a copper metal line layer covers the diffusion layer and fills the interconnect hole with a copper metal line. Perform a CMP process to planarize the device to remove copper above the IMD layer. Deposit a passivating metal layer on the surface of the copper metal line encapsulating the copper metal line at the top of the hole in a self-aligned deposition process. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/http://analytics.patsnap.com/patent_view/view?pn=US6100195 | |
dc.source | PatSnap | |
dc.type | Patent | |
dc.contributor.department | INSTITUTE OF MICROELECTRONICS | |
dc.identifier.isiut | NOT_IN_WOS | |
dc.description.patentno | US6100195 | |
dc.description.patenttype | Granted Patent | |
dc.contributor.patentassignee | CHARTERED SEMICONDUCTOR MANU. LTD. (SINGAPORE, SG) | |
dc.contributor.patentassignee | NATIONAL UNIVERSITY OF SINGAPORE (SINGAPORE, SG) | |
dc.contributor.patentassignee | NAHYANG TECHN. UNIV. OF SINGAPORE (SINGAPORE, SG) | |
dc.contributor.patentassignee | INSTITUTE OF MICROELECTRONICS | |
Appears in Collections: | Staff Publications |
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US6100195.PDF | 233.14 kB | Adobe PDF | OPEN | Published | View/Download |
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