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Title: Simulation and fabrication of an interposer for electrical testing of fine-pitch wafer-level packages
Authors: DENG CHUN
Keywords: Interposer, Nano Wafer-level Package (NWLP), Known Good Die, Probe Card, Silicon Processing, Test and Burn-in
Issue Date: 20-Aug-2004
Citation: DENG CHUN (2004-08-20). Simulation and fabrication of an interposer for electrical testing of fine-pitch wafer-level packages. ScholarBank@NUS Repository.
Abstract: This thesis describes the design, fabrication and electrical simulation of a new MEMS-based interposer which serves as the electro-mechanical interface between the device chip under test and the test processor. The interposer has vertical through wafer interconnection and capable of probing area array pins. It is designed to meet the requirement of fanning out the 100um pitch chip-to-substrate interconnections to about 750um pitch which is compatible with current printed circuit board processing technology. It has three build-up metal layers on top of a silicon substrate, in turn named power plane, ground plane and compliant structure. It is fabricated on a silicon substrate by semiconductor and micro-machining processes. Through-wafer vias are formed by potassium hydroxide anisotropic etching. Conductive materials are filled in the vias to form an interconnection. The compliant structures which give vertical compliance to the probe pads are released by XeF2. The structural characteristics of compliant structures of various geometries were evaluated using a finite element software ANSYS while the electrical characteristics were evaluated using another software HFSS. As the substrate is made of silicon, there is no thermal mismatch between chip and substrate and hence no thermal stress induced during wafer level burn-in testing. This is an important advantage of using a silicon interposer.
Appears in Collections:Master's Theses (Open)

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