TOWARD A RUNTIME PROGRAMMABLE SPIKING NEURAL NETWORK HARDWARE ACCELERATOR WITH ON-CHIP LEARNING

Abstract

Significant advances in neuroscience research have led to the emergence of Spiking Neural Networks (SNNs), energy-efficient machine learning algorithms inspired by the activities of the biological brain. Due to their event-driven nature, SNNs are expected to consume less energy than Artificial Neural Networks (ANNs). However, implementing complex SNNs that achieve satisfactory accuracy in various applications still demands substantial hardware resources, time, and energy. This thesis focuses on developing a hardware architecture and software-based methods to enable efficient implementation of SNNs with on-chip learning capability on embedded systems platforms. To achieve this objective, we propose a flexible SNN co-processor that allows runtime network reconfiguration. Moreover, a synapse pruning algorithm is introduced to reduce network complexity, resulting in significant time and energy savings on our hardware implementation. Additionally, we present a hardware-friendly semi-supervised learning scheme designed to facilitate online adaptation on embedded systems platforms.