IMPROVING PERFORMANCE OF MODERN MEMORY SUBSYSTEM

Abstract

The performance and energy efficiency of modern computing systems are largely dominated by its memory system. The memory system's performance has become critical as with the scaling of the device, the access latency of physical memory i.e. Dynamic random access memory (DRAM) has not scaled well. In the last two decades the capacity of DRAM has increased by almost 100x whereas its access latency has increased only by 30%. Hence, the memory system has become a bottleneck in improving the performance of the computing systems. The memory bottleneck has been also exacerbated by the emergence of data-intensive applications like graph analytics which has a large memory footprint and irregular memory access pattern. In order to address this memory wall challenge, this thesis aims to explore and design low cost architectural technique to reduce the data movement within the memory hierarchy by leveraging the characteristics of emerging memory technologies, and behaviour of the workloads. Thus, this thesis focuses on developing novel architectural techniques to reduce the performance penalty due to off-chip memory accesses.