ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm

Please use this identifier to cite or link to this item: https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185261

DC Field	Value
dc.title	ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm
dc.contributor.author	Joydeep Basu
dc.contributor.author	Sachin Taneja
dc.contributor.author	Viveka Konandur Rajanna
dc.contributor.author	Tianqi Wang
dc.contributor.author	Massimo Bruno Alioto
dc.date.accessioned	2023-08-15T01:17:47Z
dc.date.available	2023-08-15T01:17:47Z
dc.date.issued	2023-06-11
dc.identifier.citation	Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Bruno Alioto (2023-06-11). ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). ScholarBank@NUS Repository. https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185261
dc.identifier.isbn	978-4-86348-806-9
dc.identifier.isbn	979-8-3503-4669-5
dc.identifier.uri	https://scholarbank.nus.edu.sg/handle/10635/244206
dc.rights	CC0 1.0 Universal
dc.rights.uri	http://creativecommons.org/publicdomain/zero/1.0/
dc.type	Conference Paper
dc.contributor.department	ELECTRICAL AND COMPUTER ENGINEERING
dc.description.doi	10.23919/VLSITechnologyandCir57934.2023.10185261
dc.description.sourcetitle	2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
dc.published.state	Published
Appears in Collections:	Elements Staff Publications

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