RELIABILITY CHARACTERIZATION AND MODELING FOR HIGH VOLTAGE LDMOS DEVICES

Abstract

This research is focused on the reliability characterization and modeling for high voltage (HV) power devices such as lateral double-diffusion MOSFET (LDMOS) and extended-drain MOSFET (EDMOS). HV power devices are widely used in ranges of flat panel display, automotive and smart power applications at baseband, radio frequency (RF) and millimeter wave. The main physical mechanisms for the degradation of logic low voltage (LV) MOSFET transistors are hot carrier injection (HCI), bias temperature instability (BTI) and time dependent dielectric breakdown (TDDB). However, due to structural and functional difference, there are more degradation mechanisms introduced in HV MOSFET. The drift region resistance degradation leads to different device degradation rate at both linear and saturation region stress region. And there are negative degradation and off-state degradation in HV MOSFET as well. This research developed an accurate Aging model for HV MOSFET based on physics, and it can be applied to circuit Aging performance prediction.