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https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830250
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dc.title | Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing | |
dc.contributor.author | Umesh Chand | |
dc.contributor.author | Mohamed M Sabry Aly | |
dc.contributor.author | Manohar Lal | |
dc.contributor.author | Chen Chun-Kuei | |
dc.contributor.author | Sonu Hooda | |
dc.contributor.author | Shih-Hao Tsai | |
dc.contributor.author | Zihang Fang | |
dc.contributor.author | Hasita Veluri | |
dc.contributor.author | Aaron Voon-Yew Thean | |
dc.date.accessioned | 2022-10-12T01:37:36Z | |
dc.date.available | 2022-10-12T01:37:36Z | |
dc.date.issued | 2022-06-12 | |
dc.identifier.citation | Umesh Chand, Mohamed M Sabry Aly, Manohar Lal, Chen Chun-Kuei, Sonu Hooda, Shih-Hao Tsai, Zihang Fang, Hasita Veluri, Aaron Voon-Yew Thean (2022-06-12). Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) : 326-327. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830250 | |
dc.identifier.isbn | 978-1-6654-9773-2 | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/232258 | |
dc.description.abstract | For the first time, we investigated ultra-short-channel ZnO thin-film FETs with Lch = 8 nm with extremely scaled channel thickness tZnO of 3nm, the device exhibits ultra-low sub-pA/µm off leakage (1.2 pA/µm), high electron mobility (µeff = 84 cm2/V•s) with record peak transconductance (Gm,) of 254 μS/μm at VDS = 1 V wrt. reported oxide-based transistors, to date, leading to high on-state current (ION) of 561 μA/μm. We demonstrated the integration of a ZnO access transistor with Al2O3 RRAM to enable a 1T-1R memory cell, suitable for BEOL-embedded memory. We evaluate the system-level benefits of a hardware accelerator for deep learning to employ FET-RRAM as working memory—up to 10X energy-efficiency benefits can be achieved over current baseline configurations. | |
dc.language.iso | en | |
dc.publisher | IEEE | |
dc.rights | CC0 1.0 Universal | |
dc.rights.uri | http://creativecommons.org/publicdomain/zero/1.0/ | |
dc.type | Conference Paper | |
dc.contributor.department | DEAN'S OFFICE (ENGINEERING) | |
dc.contributor.department | ELECTRICAL AND COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/VLSITechnologyandCir46769.2022.9830250 | |
dc.description.sourcetitle | 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) | |
dc.description.page | 326-327 | |
dc.published.state | Published | |
dc.grant.id | RSS2015-003 | |
dc.grant.fundingagency | This work was supported by Agency for Science, Technology and Research (A*STAR), Singapore under its AME Programmatic Funds (A1892b0026 and A18A1B0045), National Research Foundation Grant RSS2015-003, and the Singapore Hybrid-Integrated Next-Generation μ-Electronics (SHINE) Centre hosted at the National University of Singapore (NUS). | |
Appears in Collections: | Staff Publications Elements |
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Sub-10nm_Ultra-thin_ZnO_Channel_FET_with_Record-High_561_A_m_ION_at_VDS_1V_High_-84_cm2_V-s_and1T-1RRAM_Memory_Cell_Demonstration_Memory_Implications_for_Energy-Efficient_Deep-Learning_Computing.pdf | 1.96 MB | Adobe PDF | CLOSED | None |
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