Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830250
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dc.titleSub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing
dc.contributor.authorUmesh Chand
dc.contributor.authorMohamed M Sabry Aly
dc.contributor.authorManohar Lal
dc.contributor.authorChen Chun-Kuei
dc.contributor.authorSonu Hooda
dc.contributor.authorShih-Hao Tsai
dc.contributor.authorZihang Fang
dc.contributor.authorHasita Veluri
dc.contributor.authorAaron Voon-Yew Thean
dc.date.accessioned2022-10-12T01:37:36Z
dc.date.available2022-10-12T01:37:36Z
dc.date.issued2022-06-12
dc.identifier.citationUmesh Chand, Mohamed M Sabry Aly, Manohar Lal, Chen Chun-Kuei, Sonu Hooda, Shih-Hao Tsai, Zihang Fang, Hasita Veluri, Aaron Voon-Yew Thean (2022-06-12). Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing. 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) : 326-327. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830250
dc.identifier.isbn978-1-6654-9773-2
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/232258
dc.description.abstractFor the first time, we investigated ultra-short-channel ZnO thin-film FETs with Lch = 8 nm with extremely scaled channel thickness tZnO of 3nm, the device exhibits ultra-low sub-pA/µm off leakage (1.2 pA/µm), high electron mobility (µeff = 84 cm2/V•s) with record peak transconductance (Gm,) of 254 μS/μm at VDS = 1 V wrt. reported oxide-based transistors, to date, leading to high on-state current (ION) of 561 μA/μm. We demonstrated the integration of a ZnO access transistor with Al2O3 RRAM to enable a 1T-1R memory cell, suitable for BEOL-embedded memory. We evaluate the system-level benefits of a hardware accelerator for deep learning to employ FET-RRAM as working memory—up to 10X energy-efficiency benefits can be achieved over current baseline configurations.
dc.language.isoen
dc.publisherIEEE
dc.rightsCC0 1.0 Universal
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/
dc.typeConference Paper
dc.contributor.departmentDEAN'S OFFICE (ENGINEERING)
dc.contributor.departmentELECTRICAL AND COMPUTER ENGINEERING
dc.description.doi10.1109/VLSITechnologyandCir46769.2022.9830250
dc.description.sourcetitle2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
dc.description.page326-327
dc.published.statePublished
dc.grant.idRSS2015-003
dc.grant.fundingagencyThis work was supported by Agency for Science, Technology and Research (A*STAR), Singapore under its AME Programmatic Funds (A1892b0026 and A18A1B0045), National Research Foundation Grant RSS2015-003, and the Singapore Hybrid-Integrated Next-Generation μ-Electronics (SHINE) Centre hosted at the National University of Singapore (NUS).
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