NON-VOLATILE IN-MEMORY COMPUTING WITH SKYRMIONS AND PHASE CHANGE MEMORIES

Abstract

The non-volatile in-memory compute engine (NVIMCE), which saves on the latency and energy associated with data movement between memory and processing elements in the conventional von Neumann architectures, is a crucial design technique for enabling ultra-low power intelligent edge devices. Due to power/area versus throughput trade-offs (such as to increase the complexity of periphery circuitry to enable higher parallelism or result precision), the memory subsystem in NVIMCE needs to be carefully designed to avoid incurring large power and area overheads. Furthermore, the emerging non-volatile memory technologies that are suitable for application in NVIMCE suffer from issues such as read/write errors, low endurance, and cycle-to-cycle variations. Hence, this dissertation addresses key design issues using a device-circuit-architecture co-design framework and demonstrates promising design strategies for NVIMCEs using skyrmions and phase-change memories. The proposed design strategies achieved ultra-low power consumption and low latencies needed for future edge devices in Internet of Smart Things.