Please use this identifier to cite or link to this item: https://doi.org/10.1109/S3S46989.2019.9320502
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dc.titleDesign and Study of an Artificial Spiking Neuron Enabled by Low-Voltage SiOx-based ReRAM
dc.contributor.authorNIU XUHUA
dc.contributor.authorLI YIDA
dc.contributor.authorTHEAN VOON YEW, AARON
dc.date.accessioned2021-06-14T02:07:04Z
dc.date.available2021-06-14T02:07:04Z
dc.date.issued2021-01-20
dc.identifier.citationNIU XUHUA, LI YIDA, THEAN VOON YEW, AARON (2021-01-20). Design and Study of an Artificial Spiking Neuron Enabled by Low-Voltage SiOx-based ReRAM. 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). ScholarBank@NUS Repository. https://doi.org/10.1109/S3S46989.2019.9320502
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/192010
dc.description.abstractIn this paper, we study the implementation of a SiO x ReRAM an artificial spiking neuron network (SNN) as a memristive synapse. The analog switching SiO x based resistive random access memory (ReRAM) uses room temperature process and switches at sub 1.2V, suitable for BEOL integration. We analyze the neuron circuit speed impact from ReRAM switching, supply voltage and power consumption. With an single industry I/O voltage of +1.8V besides necessary negative supply for bipolar signal generation, and by co-optimizing the neuron circuit in the region of μs, the operating speed can be 3 orders faster than existing reported SNN circuit. In addition, we show that the ReRAM switching time poses the speed bottleneck for the SNN circuit. In order to further enhance the SNN operating speed, improvement to the ReRAM switching time is needed, or the need to increase the voltage supply but at the expense of power consumption.
dc.description.urihttps://ieeexplore.ieee.org/document/9320502
dc.language.isoen
dc.publisherIEEE
dc.rightsCC0 1.0 Universal
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/
dc.subjectSpiking Neural Network, Resistive Random Access Memory, Spike-Timing-Dependent Plasticity
dc.typeArticle
dc.contributor.departmentELECTRICAL AND COMPUTER ENGINEERING
dc.description.doi10.1109/S3S46989.2019.9320502
dc.description.sourcetitle2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
dc.published.statePublished
dc.grant.idNRF-RSS2015-003
dc.grant.fundingagencyNRF
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