Please use this identifier to cite or link to this item: https://doi.org/10.1109/JSSC.2021.3050959
DC FieldValue
dc.titlePUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion
dc.contributor.authorSACHIN TANEJA
dc.contributor.authorALIOTO,MASSIMO BRUNO
dc.date.accessioned2021-05-14T02:12:53Z
dc.date.available2021-05-14T02:12:53Z
dc.date.issued2021-03-02
dc.identifier.citationSACHIN TANEJA, ALIOTO,MASSIMO BRUNO (2021-03-02). PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. IEEE Journal of Solid-State Circuits : 1 - 1. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2021.3050959
dc.identifier.issn00189200
dc.identifier.issn1558173X
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/191221
dc.description.abstract"This work introduces a novel class of fully-synthesizable all-digital True Random Number Generators (TRNGs) using the same private-key cryptographic core for raw dynamic entropy generation, its extraction via post-processing, and its utilization as crypto-key for constrained secure systems. Endogenous random bit generation is achieved via clock pulsewidth overstretching in the digital implementation of private-key cryptographic algorithms using pulsed-latch pipelines, leveraging inherent Shannon confusion and diffusion. Demonstration on a 40-nm testchip based on a SIMON cryptographic core shows 64-bit key encryption down to 0.25 pJ/bit at 0.45 V, random number generation with cryptographic-grade entropy at 2.5 pJ/bit across manufacturing lots, dice, voltages and temperature corners. The overall area is kept well below the 1E6 F2 area wall (F = minimum feature size).
dc.language.isoen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.rightsCC0 1.0 Universal
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/
dc.subjectPhysically unclonable function
dc.subjectresilient circuits
dc.subjectrun-time adaptation
dc.subjectsensor fusion
dc.subjectenergy efficiency
dc.typeArticle
dc.contributor.departmentELECTRICAL AND COMPUTER ENGINEERING
dc.description.doi10.1109/JSSC.2021.3050959
dc.description.sourcetitleIEEE Journal of Solid-State Circuits
dc.description.page1 - 1
dc.published.statePublished
dc.grant.fundingagencyNational Research Foundation Singapore
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