Please use this identifier to cite or link to this item:
https://doi.org/10.1109/JSSC.2021.3050959
DC Field | Value | |
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dc.title | PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion | |
dc.contributor.author | SACHIN TANEJA | |
dc.contributor.author | ALIOTO,MASSIMO BRUNO | |
dc.date.accessioned | 2021-05-14T02:12:53Z | |
dc.date.available | 2021-05-14T02:12:53Z | |
dc.date.issued | 2021-03-02 | |
dc.identifier.citation | SACHIN TANEJA, ALIOTO,MASSIMO BRUNO (2021-03-02). PUF Architecture with Run-Time Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion. IEEE Journal of Solid-State Circuits : 1 - 1. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2021.3050959 | |
dc.identifier.issn | 00189200 | |
dc.identifier.issn | 1558173X | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/191221 | |
dc.description.abstract | "This work introduces a novel class of fully-synthesizable all-digital True Random Number Generators (TRNGs) using the same private-key cryptographic core for raw dynamic entropy generation, its extraction via post-processing, and its utilization as crypto-key for constrained secure systems. Endogenous random bit generation is achieved via clock pulsewidth overstretching in the digital implementation of private-key cryptographic algorithms using pulsed-latch pipelines, leveraging inherent Shannon confusion and diffusion. Demonstration on a 40-nm testchip based on a SIMON cryptographic core shows 64-bit key encryption down to 0.25 pJ/bit at 0.45 V, random number generation with cryptographic-grade entropy at 2.5 pJ/bit across manufacturing lots, dice, voltages and temperature corners. The overall area is kept well below the 1E6 F2 area wall (F = minimum feature size). | |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
dc.rights | CC0 1.0 Universal | |
dc.rights.uri | http://creativecommons.org/publicdomain/zero/1.0/ | |
dc.subject | Physically unclonable function | |
dc.subject | resilient circuits | |
dc.subject | run-time adaptation | |
dc.subject | sensor fusion | |
dc.subject | energy efficiency | |
dc.type | Article | |
dc.contributor.department | ELECTRICAL AND COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/JSSC.2021.3050959 | |
dc.description.sourcetitle | IEEE Journal of Solid-State Circuits | |
dc.description.page | 1 - 1 | |
dc.published.state | Published | |
dc.grant.fundingagency | National Research Foundation Singapore | |
Appears in Collections: | Staff Publications Elements |
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File | Description | Size | Format | Access Settings | Version | |
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Run-Time PUF Adaptation for Resilient and Energy-Efficient Key Generation via Sensor Fusion and Machine Learning.pdf | 896.09 kB | Adobe PDF | OPEN | Post-print | View/Download |
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