Crossing the resolution limit in near-infrared imaging of silicon chips: Targeting 10-nm node technology

Abstract

The best reported resolution in optical failure analysis of silicon chips is 120-nm half pitch demonstrated by Semicaps Private Limited, whereas the current and future industry requirement for 10-nm node technology is 100-nm half pitch. We show the first experimental evidence for resolution of features with 100-nm half pitch buried in silicon (?/10.6), thus fulfilling the industry requirement. These results are obtained using near-infrared reflection-mode imaging using a solid immersion lens. The key novel feature of our approach is the choice of an appropriately sized collection pinhole. Although it is usually understood that, in general, resolution is improved by using the smallest pinhole consistent with an adequate signal level, it is found that in practice for silicon chips there is an optimum pinhole size, determined by the generation of induced currents in the sample. In failure analysis of silicon chips, nondestructive imaging is important to avoid disturbing the functionality of integrated circuits. High-resolution imaging techniques like SEM or TEM require the transistors to be exposed destructively. Optical microscopy techniques may be used, but silicon is opaque in the visible spectrum, mandating the use of near-infrared light and thus poor resolution in conventional optical microscopy. We expect our result to change the way semiconductor failure analysis is performed.