RAMAN SCATTERING OF TITANIUM SILICIDE

Abstract

With device scaling down to the deep sub-micron regime, the titanium (Ti) self-aligned silicide (SALICIDE) contact technology has increasingly become an integral part of high performance CMOS devices. It is used to lower the sheet resistance of the gate and source/drain regions contact and series resistance, thus lowering the RC delays to allow for faster operation and increasing the device performance. Development of the Ti-SALICIDE process takes into strong consideration device parameters such as the sheet resistance of the gate and source/drain regions, the junction and gate-to-source/drain leakage currents. Hence, an easy and reliable characterization method needs to be present to check for process capability and uniformity. Methods such as electrical sheet resistance measurement and material structural characterization by X-ray diffraction have been developed, but these posed drawbacks such as sample destruction and lack of spatial resolution, and more importantly, the difficulty in using these tools for in-line SALICIDE process monitoring, especially for devices with deep sub-micron geometry. In this project, the feasibility of using micro-Raman spectroscopy as an in-line monitoring tool for Ti-SALICIDE processing is probed. The focus is centered on the characterization of the low resistivity C54 phase of TiSi2, which is formed from its higher resistivity C49 phase. Initial studies were made on TiSi2 formed from a standard four step SALICIDE process, namely (a) an initial blanket Ti sputter deposition, (b) formation of the high resistivity C49 phase using rapid thermal annealing at ~ 690 °C in N2 ambient, (c) SALICIDE etchback using wet etch, and (d) transformation of the C49 to the C54- TiSi2 phase using a second rapid thermal annealing at ~ 850 °C. Due to the distinct crystal structures of the C49 and C54- TiSi2, micro-Raman spectroscopy could differentiate the two phases clearly. Making use of the Raman intensity of the C54-TiSi2 peak, a methodology for characterizing the formation, transformation and agglomeration of TiSi2 was developed in this project. Results were shown to have good correlation with the electrical sheet resistance. The second part of the project extends the micro-Raman and electrical sheet resistance characterizations to silicides formed using newer SALICIDE schemes, namely (a) Si implant TiSi2, where an extra Si implant step is carried out immediately after Ti deposition, and (b) chemical vapour deposited (CVD) TiSi2. The method developed previously using micro-Raman for process characterization was again demonstrated to give reliable result that correlates well with electrical sheet resistance measurements. Results show that the Si implant TiSi2 scheme provides a lower and wider process window for the SALICIDE process, which is advantageous for current integrated circuits processing since thermal budget must be kept to a minimal. The last part of the project involves fabrication and analysis of CMOS transistors using process conditions for SALICIDE formation based on previous micro-Raman and electrical studies. Three different SALICIDE schemes were used, namely (a) a single 400 Å Ti layer, (b) a Ti (450Å) / TiN (150Å) bilayer, and (c) Si implant through metal (Ti) SALICIDE. Transistor electrical parameters that depended heavily on the silicidation process, ie. (a) narrow poly-Si gate sheet resistance, (b) gate-to-source/drain current leakage, and (c) transistor junction leakage current was analyzed. The Si implant SALICIDE scheme gave well controlled sheet resistance, with nominal value of ~ 3 ?/sq, unlike the other 2 SALICIDE schemes, which gave larger spread. The gate-to-source/drain leakage of all the transistors were comparable, with the n- and p-MOSFET giving ~ 0.018 nA (1.18 ƒA/µm) and ~ 0.021 nA (1.38 ƒA/µm), respectively. For the jm1ction leakage, it was observed that p-MOS was less susceptible to process condition changes, with average value of- 0.07 nA (2.89 ƒA/µm) for all the p-MOS transistors. For then-MOS, the Si implant SALICIDATION scheme with 1 x 10 15 cm-2 dose at 40 keV gave the lowest junction leakage ~ 0.015 nA (0.62 ƒA/µm). The biasing voltages used were 3.6 V for voltage high and 0 V for common ground.