VLSI IMPLEMENTATION OF TRANSFORM DOMAIN ADAPTIVE FILTERS

Abstract

In this research project, the architecture of a digital signal processor is designed and implemented in VLSI.The processor is tailored for effective implementation of transform domain adaptive filters (TDAF). It is called Generalized Sliding Transform processor ( GST processor) since it can be used for the implementation of a class of transforms called Generalized. Sliding Transform. The commonly used transforms, such as Discrete Fourier transform (DFT) and Walsh Hadamard Transform (WHT) when their length is a power of 2 belong to this class of transformations. The GST processor has adequate hardware and instruction set to implement different types of TDAF's. In particular, it can be used for the implementation of the Frequency Domain Block LMS (FBLMS) adaptive filters. The GST processor performs the calculations in fixed point 24-bits. The GST processor incorporates a butterfly processor which is able to perform butterfly and inverse butterfly operations that are essential in the implementation of FFT and other transformations commonly used in TDAF's. Through the same operations, it is also able to implement complex and real multiplication as well as addition and subtraction. It makes use of a recently developed binary tree multiplier with singed-digit encoding which reduces the number of levels in the tree by 1. The multiplier's inputs are 16-bit and 24-bit wide. The butterfly processor is able to directly access the memory. This is provided to increase the efficiency of the memory access. The GST processor incorporates an ALU to perform integer arithmetic and address calculations. Moreover, an efficient method to implement the Generalized Sliding Transform is to use a circular memory scheme. In order to implement this scheme, the ALU is equipped with suitable hardware. The GST processor implements the essential variables of the FBLMS structure in registers of a register file to increase the efficiency of the algorithm. Most of the registers, however, can be used for other purposes as well. The GST processor incorporates two output data buses and one input data bus to the register file. Therefore, it is possible to implement instructions with three operands, two of which are input and the other one is output. The type of Generalized Sliding Transform is determined by an on-chip ROM called the transformation coefficients memory. The ROM contains the coefficients of FFT for the case where the length of transform is 512. However, the same coefficients can be used to perform FFT of lengths less than that. This can be obtained by simply skipping the unnecessary coefficients. By changing the coefficients appropriately, any other Generalized Sliding Transform can be implemented. Addressing and address calculation of the ROM is performed independent of the ALU to enable the processor to perform another instruction while the ROM is being accessed.