HOT-CARRIER EFFECTS IN THIN GATE OXIDE MOSFET'S

Abstract

As current VLSI fabrication technology pushes towards deep sub-micron devices, hot-carrier degradation in transistors needs to be revisited. Since the reduction of gate oxide thickness is a very important step in device miniaturization, we can gain insights into the degradation mechanisms in deep sub-micron MOSFET's by studying the hot-carrier degradation in very thin gate oxide (50 Å) devices. The impact ionization rate in thin (50 Å) and thick (125 Å) gate oxide n-MOSFET's was investigated. The impact ionization rate in thin gate oxide n-MOSFET's is lower at 77 K compared to that at 300 K for the same (Vd-Vdsat). At low temperatures, the non-stationary phenomenon becomes more pronounced, particularly in the high field and field gradient regions of thin gate oxide devices. This causes a reduction in impact ionization rate. A modified lucky-electron model, which takes into account the non-stationary effects of carriers, is shown to be able to explain the observed impact ionization rate at 77 K. The model also explains the cross over of the ionization rates, for the 77 and 300 K curves in thick gate oxide devices. The surface-channel p-MOSFET's were subjected to Igmax, Isubmax Vg = Vd stress modes to investigate the hot-carrier degradation mechanisms at 79 K and 300 K. It was observed that the interface state generation increases with stress Vg, This suggests that channel hot-hole injection plays an important role in the hot-carrier degradation. In n-MOSFET's, the worst degradation occurs when the test devices are subjected to mid-Vg stress at both 79 K and 300 K. Under this stress condition, maximum impact ionization occurs. Thus, a high number of hot carriers such as avalanche hot holes and electrons are generated which can cause interface state generation. The overall degradation of p- and n-MOSFET's are more severe at low temperatures because of the higher interface state generation and the increase in the role of coulombic scattering. The post-stress interface state generation was investigated for p-MOSFET's after DAHE (drain avalanche hot electron) injection. The role of holes from Si substrate was demonstrated in our experiments. It was shown that if holes are depleted from the hot-carrier degraded Si/Si02 interface by appropriate drain or gate bias, the interface states annealed out. The results reveal a strong dependence on holes in post-stress interface state generation.