ANALYTIC METHODS FOR TIMING ANALYSIS OF INTERCONNECTS IN CMOS VERY LARGE SCALE INTEGRATED CIRCUITS

Abstract

MOSFET structures appearing in NAND, NOR or any combinational logic gates are commonly used in VLSI circuits. These gates are interconnected via long chain of metal and polysilicon lines. With the system clock speed approaching hundreds of MHz, a quick and accurate estimation of the time delay is essential. Traditionally, delay analysis was performed by representing the gates with a step voltage source and a series resistance, known as driver resistance. However these were done by either assuming the load to be purely capacitive or with no particular regard to accuracy of driver resistance. With the current advances in IC fabrication process, the minimum feature size of interconnect has greatly reduced. Also, the length of intercon­ next is increased due to the rise in complexity of circuits being designed and high level of design automation. This gives rise to increased interconnect resistance. Hence ignoring the resistive element of the interconnect leads to erroneous delay analysis. This thesis presents accurate delay analysis for n-channel and p-channel devices. It takes into consideration the source, drain and interconnect resistance. One of the important aspect of this work is that it takes into account the short channel effects, such as channel length modulation and velocity saturation, and yields analytic expression for time delay. The analytical expression is further refined to take into consideration of ramp input. This gives a highly accurate analytical delay expression to calculate the time delay for any series connected MOSFET structures driving an interconnect. The accuracy of the analytical equations is established by a very close agreement with SPICE simulation results. It is found that reduction in time delay by increasing saturation velocity diminished as the saturation velocity is increased beyond a certain value. It is also found that the rate of increase of time delay with resistive part of the load is substantially reduced with velocity saturation effect in the model. The delay prediction in case of ten inverter chain and four branch circuit with resistive and capacitive load agreed well with that from SPICE. This method, however, is much faster as there are no iterations as there are in SPICE.