MICROARCHITECTURE OF A HIGH THROUGHPUT TEXTURE MAPPING PROCESSOR FOR INTERACTIVE 3D GRAPHICS

Abstract

Texture mapping provides realistic details without producing large quantities of geometric objects in real-time applications such as animation, virtual reality, scientific visualization and interactive 3D games. An implementation of hardware texture mapping at interactive rates for the mainstream PC market, which demands a low cost but high performance 3D graphics rendering IC, is described. In particular, the scope is limited to the detailed description of the microarchitecture and implementation of a texture address processor which interpolates texture addresses (texture coordinates), called the S, T and Q parameters, with perspective correction or without correction. The processor uses digital differential analyzers (DDA), during span interpolation of a triangle, to calculate the texel addresses of the texture map. Subpixel correction is implemented inexpensively by means of the addition or subtraction of partial products instead of a full multiplication. Perspective correction with per-pixel division of mapped textures is implemented with a cellular array divider providing a reciprocal function and two array multipliers. The processor can be used to scale, rotate and warp images. Various techniques are applied to the design of the processor to achieve a peak throughput of 100 million texture mapped pixels per second. Changes to the basic backend rendering architecture to achieve twice this peak throughput is also described. The texture address processor is realized at 100 MHz in a 3D graphics rendering IC which will be fabricated in a 0.25 µm CMOS technology. A generic schema for the design of processors with DDA circuits has been developed and applied to the design of the texture address processor. The processor decodes and executes instruction-data pairs from a 2-word deep input FIFO. Instructions may cause an interpolation in the S, T and Q DDAs. A single cycle decode-execute DDA controller controls all three DDA datapaths in parallel. Instructions may also initiate a computation in a dynamically configured pipeline to compute the perspective uncorrected, clamped S and T texture coordinates or the perspective corrected S/Q and T/Q values. The perspective uncorrected pipeline has only one pipe stage register. The perspective division pipeline is implemented as a restoring cellular array divider and two array multipliers and has 5 pipe stage registers. An 8-word deep FIFO, operating in parallel with the dynamic pipeline, provides buffering of instruction-data pairs and control information. The output section of the processor decodes and executes instructions in order from this FIFO, and forwards results from the dynamic pipeline and instruction-data pairs to a 2-word deep output FIFO. The performance of the processor is improved by minimizing the achievable latency of the processor e.g. by providing the internal 8-word FIFO, realizing the functional datapaths as physical datapaths with minimum wire delays, and realizing a dynamically configured computational pipeline instead of a static pipeline. In comparison with an existing texture address processor designed for 50 MHz, this design showed a reduction of 41 % in the number of clock cycles for texture address computation at the same clock period.