RELIABILITY CHARACTERIZATION OF MOS TRANSISTORS USING THE DRAIN CURRENT CONDUCTANCE METHOD

Abstract

Over the past decade, the advancement in fine-line patterning technologies had resulted in the decrease of MOS devices dimensions. The continual scaling of MOS devices to deep-submicrometer dimensions has the advantage of increasing the packing density of each silicon chip. However, the reliability of these advanced devices has always been a major concern. The hot-carrier induced degradation of MOS transistors is one of the primary concerns. Several MOS transistors structures have been proposed to minimise the hot-carrier effect. In this work, the characterisation of these graded junction devices using a previously developed Drain Current Conductance Method (DCCM) technique was carried out. The DCCM technique was further improved to include the effect of substrate back-biasing in this work. The improved technique is able to extract parameters of devices with a physical mask gate length down to 0.35 µm. The DCCM technique was applied to extract the gate-bias dependent effective channel mobility (µeff) of MOS transistors with plasma-induced damage. The results show that µeff decreases with increasing antenna ratio. Therefore, µeff is a good monitor for the quality of the Si-SiO2 interface. This method is simple and effective, making it highly attractive for in-process plasma-induced damage characterisation. A three-stage hot-carrier degradation in drain-engineered NMOSFETs was observed. This phenomenon is explained by using a physical model based on drain series resistance (Rd) and µeff degradation. The damage starts at the spacer region and proceeds towards the channel region as stress time increases. A two-dimensional device simulation was performed to verify the three-stage degradation observation. Although the previously developed DCCM technique is able to extract the gate-bias dependent effective channel mobility and the series resistances (Rd, Rs), it does not include the effect of the substrate back-biasing. In this work, the DCCM technique was improved to assist in the investigation of the back-bias effect on LATID NMOSFETs. For the same effective gate overdrive, the extracted drain and source series resistances increase as the back-bias is increased. Two-dimensional device simulation showed that as the back-bias is increased, the current contour values at the drain/source region are reduced as a result of the increase in the series resistances.