PACKAGE CRACKING MECHANISM IN PLASTIC ENCAPSULATED INTEGRATED CIRCUIT DEVICES

Abstract

Cracking of integrated circuit (IC) packages is mainly due to excessive iNtemal stress caused by thermal mismatch between the different materials constituting the package. There are known to be 3 modes of failure in fracture mechanics : opening mode I, shearing mode II and sliding mode III. Failure of IC packages are usually of modes I and II. Stress concentration occurs at the comers of ship, pad and leads inside IC packages, and it is well known that package cracks usually proceed from them. At these locations, the stress level is extremely high and difficult to determine accurately even using finite element analysis. Thus, a failure criterion based on stress level alone is likely to be inadequate. However, using linear elastic fracture mechanics theory, it is possible to use the stress intensity factor, K, and the associated energy release rate, G, as failure criteria. K and G are easily obtained from a finite element stress analysis of the IC package. While K may be easily computed for a package undergoing a thermal stressing process, a critical K value is required in order to determine whether the package will fail. It is proposed that this critical K value is the one obtained in the commonly conducted adhesion (pull) test. In other words, an adhesion test is carried out to measure the maximum force required to pull a strip of pad material embedded in a block of the particular moulding compound which has been subjected to the same thermal stressing conditions. A finite element analysis is then performed on the pull test specimen to determine the maximum stress intensity factor Kc corresponding to the measured maximum strength. This Kc is then the critical value for the moulding compound under the particular environmental condition. If the maximum K value obtained for the package exceeds the critical value Kc, then delamination will occur.

The mechanism of cracking of IC packages is known to occur over 3 stages. The first stage is the delamination initiation stage caused by thermal mismatch as discussed above. The second stage is the delamination growth. The driving force behind this growth is the vapour pressure. Moisture has been absorbed into IC packages from the environment. Due to the high temperature of the solder reflow process, the moisture will expand and thus cause the delamination to grow until the interface between chip pad and moulding compound is fully delaminated. The analysis of this stage is based on beam theory. After this stage is completed, the final stage will begin with a crack initiation in the moulding compound. This crack initiation point is the same point as the delamination initiation point. Once a crack is initiated, it will propagate outward until it reaches the outer surface of the IC package. The criterion for the crack initiation is again based on fracture mechanics. In this case, the strain energy release rate of the IC package is calculated. It is then compared with a critical value for the mould compound which is measured in accordance with an American Standard for the testing of materials (ASTM). In order to confirm the accuracy of the above predictions, actual package specimens were fabricated and subjected to several environmental conditions. The specimens were examined for delamination and cracking after vapour phase reflow. It was found that the experimental and the predicted results agree very well. The implications of the findings of this study are far-reaching. It means more than just having the capability of predicting whether a particular mould compound is suitable for a particular IC device. One can actually specify the combinations of the values of critical properties of the moulding compound which would be suitable for a particular IC device. This would give mould compound manufacturers, for the first time, a very quick means of determining if any of their existing compounds are suitable for a particular application, and possibly a systematic way of customising compounds to suit a particular IC device.