AN ACCURATE DELAY MODEL FOR BICMOS/CMOS LOGIC GATES

Abstract

VLSI technology is integrating increasingly more digital and analog functions in a single chip. Different technologies such as Bipolar, CMOS, are now integrated onto one chip. There is hence an urgency in the Computer Aided Design (CAD) community to find efficient yet accurate transient simulation techniques to verify the correctness of circuit design and guarantee the timing specifications of the systems. This thesis explores fast timing simulation for BiCMOS gates and CMOS gates. To meet the requirements of modern technologies in the submicron regions, the basic MOS transistor model used throughout this work is the Nth power MOS model. This semi-empirical model, developed by Sakurai and Newton[26][27], includes many short channel effects of submicron devices and is yet computationally efficient. The new delay model is first established on the BiCMOS invertor with the resistance-capacitance load. Using the Sakurai-Newton MOS model to accurately account for short channel effects, an analytical BiCMOS delay model is derived. The interconnect resistance is considered by using the RC load. The resulting waveforms have been compared with the SPICE simulations. A good match between the new delay model and SPICE results is observed. The new delay model is also extended to the series-connected gates. Due to the fact that VLSI systems use many kinds of complex gates, there is a stronger demand for a delay model to account for the series-connected devices. The new BiCMOS delay model that is suitable for logic gates is presented. The results of the new delay model and SPICE simulation are compared, and the accurate model of logic gates is established. Besides the series-connected gates, the input slope effect for BiCMOS gates is also considered. The input slope effect is critical for timing estimation of gate chains. Beyond the delay model for BiCMOS, a CMOS delay model for a C-R-C load is also presented. The C-R-C load gives a more accurate representation of the interconnection effect than the RC load. In all, the new delay model has been proved to be accurate over the wide range of conditions, such as different resistance, capacitance loads, logic gates and input slopes.