STATIC CURRENT AND VOLTAGE TECHNIQUES FOR CMOS RELIABILITY CHARACTERIZATION

Abstract

Many methods have been developed to characterize the reliability of integrated circuits in the past years. A static current method - the direct-current current-voltage (DCIV) method - has recently developed. A complete base current model is proposed here for the DCIV method on both LDD and non-LDD pMOSFET's. In the plot of the base current versus the gate voltage, there are two peaks, corresponding to the recombination current via interface traps in the channel region and in the LDD region, respectively. The stress-induced oxide charge shifts the peaks while the interface trapped charged causes a spread of the peaks. The peak height versus the forward emitter bias is used to evaluate the energy dependence of interface trap density. A new direct-current voltage-voltage (DCVV) method is developed to distinguish stress-induced interface traps at the drain side from those at the source side. The new method can detect a single effective interface trap at the drain nor source side. It is also found that both the DCTV method and the variable base-level charge-pumping method probe the same interface traps in pMOSFET's. Hot-carrier degradation and oxide degradation are two important reliability concerns for CMOS devices. Using the DCIV method, new results of both interface trap and oxide charge generations during device degradation are reported. The interface traps generated in the LDD region are located in a very narrow region, whose spatial location depends on the drain avalanche hot-carrier injection condition. It is inferred that the formation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced natural electron traps. For long stress times, electrons mainly fill the stress-induced electron traps. Interface trap generation by both Fowler-Nordheim (FN) electron injection and substrate hot-hole injection obeys a power-law relation with injected fluence. However, the hole injection has a smaller power exponent than the electron injection. Plasma charging damage is a serious concern for advanced silicon ULSI manufacturing. Conventionally, shifts in the device parameters were used to monitor this damage. When the oxide thickness is further scaled down in state-of-art CMOS technology, these conventional methods are no longer sensitive. It is demonstrated that the DCIV method is a powerful method in monitoring the plasma charging damage in ultra thin gate oxides.