HIGH SPEED, HIGH RESOLUTION COMPARATOR FOR A/D APPLICATIONS

Abstract

The main objective of this project is to design a high speed and high resolution comparator to be used in A/D converters. Recent developments in the field of data communications and multimedia has created a need for more mixed signal circuits. Most of the processing in a chip is digital, while the inputs and outputs to outside world is predominantly analog signals. This is the reason why data converters are invariably used as the front end of mixed signal circuits. There are a wide variety of A/D converter architectures available. A particular architecture is chosen based on the speed and accuracy that the A/D converter has to provide. An A/D converter primarily consists of a sample-holu amplifier and a comparator. The speed and accuracy of the particular A/D converter is limited by these building blocks. The objective of this project is to design a suitable comparator for high speed, high resolution A/D converters. Various comparator configurations are available. The parameters that affect the performance of a comparator are investigated and special attention is focused on the most predominant parameter. The investigation shows that the offset voltage VOFF ls a big limitation. Offset voltage is inherently present in all operational amplifiers. A comparator consists of such a high gain amplifier and a latch circuit to generate CMOS compatible outputs. A novel method of offset reduction is investigated and successfully implemented in this comparator design. This technique involves storing the offset voltage in one clock cycle and subsequently subtracting this stored offset voltage from the input voltage in the next cycle. This results in very low offset and high accuracy.