DESIGN OF COMPOUND SEMICONDUCTOR HETEROJUNCTION BIPOLAR TRANSISTORS (HBTS) FOR IMPROVED DEVICE PERFORMANCE

Abstract

The design of the step-graded collector structure of InP/InGaAs/InP DHBTs has been investigated for high current and high voltage applications. It has been shown that the collector carrier blocking effect can be most effectively minimized using an equal band gap offset ΔEg scheme in the choice of the step-graded quaternary InGaAsP layers inserted between the InGaAs and the InP regions. The larger the number of step-graded quaternary InGaAsP layers used, the less significant is the carrier blocking effect, and the larger is the maximum attainable collector current. It has also been demonstrated that a thin n-doped InP layer located near the InGaAsP/InP hetero-interface helps the electron transport through the collector region, as it lowers all the conduction band potential spikes within the collector region. An optimized collector structure has been proposed. It comprises a 100 Å n·-doped InGaAs spacer, three step-graded lnGaAsP layers (EgQ1= 0.90eV, EgQ2= 1.05eV and EgQ3=1.25eV), a l00 Å n-doped (3 x 10^17 cm^-3 ) InP layer near the InGaAsP/InP hetero-interface and a 1800 Å unintentionally n·-doped InP layer with a total collector thickness of 2600 Å.