A SLOW FREQUENCY HOPPING TRANSCEIVER MODULE SUITABLE FOR WIRELESS LINK IN THE ISM BAND

Abstract

In a Frequency Hopping (FH) system, the carrier frequency is made to hop to achieve a spread spectrum communication link. It may be a slow or fast hopper. In many applications, the carrier frequency is generated by a Phase lock loop (PLL) frequency synthesizer. The requirements of a fast switching time and a large modulation bandwidth of a phase lock loop usually are conflicting design requirements. This results in expensive system cost and hence is not so suitable for consumer electronics. In this project, a new architecture of a slow frequency hopping transceiver is proposed and a prototype built to evaluate the performance of this system. In this new architecture, the two conflicting requirements are separated by the use of a transmitter up mixer. The carrier frequency is generated by a PLL which only has a switching speed requirement. The data modulation is done in a lower frequency transmitter IF by a low frequency PLL. This effectively separates the two requirements to two PLL loops. In order to use this single hopping carrier concept, the receiver which is a dual conversion super heterodyne receiver will need to make use of the same high frequency PLL to generate its LO to bring it down to its Ifs. With digital data transmission, this is made possible by the use of Time Division Duplex (TDD) technique in which the two way communication is achieved by using the same carrier but at a time multiplex manner. This architecture greatly reduced the overall cost of the transceiver and hence it is possible to be used in consumer electronics such as a cordless phone