DEVELOPMENT OF A STATE TRANSITION DIAGRAM-BASED PROGRAMMABLE LOGIC CONTROLLER

Abstract

Traditionally, the programmable logic controller (PLC) is often programmed using ladder diagram to provide a simple transition from real relay panels to microcomputer based controls in the factory. Unfortunately, the ladder diagram suffers from the same limitations that are inherent in relay panels. It is difficult to check programs in relay logic to verify that systems will operate as intended . There have since been great strides made in improving the programming languages for the PLC. However, these developments, though making the PLC user-friendly, have not apparently addressed the fundamental issue of correctness and completeness of the design solution. This thesis describes an approach in which the specifications are entered into a PLC via a state transition diagram (STD). The use of state transition diagrams provides a rigorous framework for specification and programming and the programmer's emphasis shifts from implementation (how to arrange contacts and coils) to definition (what does the system do and when does it do it). However, the STD specification is neither exhaustive nor complete. To achieve a correct and complete design, resort is made to formal sequential logic design techniques which are tailored to the PLC application. An area of contribution made here is the verification that the system specifications entered by the programmer correspond to the requirements of the problem statement. Also, to tackle a complex control problem, the concept of functional system decomposition was applied to break a large problem into smaller and simpler modules that can be easily handled by the programmer. A PC-based software has been developed to aid in PLC-design incorporating all the above features. Diagnostic help facilities are provided to aid the programmer in achieving a complete and correct STD. An illustrative example is given to demonstrate how the problem can be broken into different levels of hierarchy of STDs. These STDs are entered independently into the system and the programmer can then verify the output for completeness and correctness before ladder diagrams are generated.