Strain Engineering for Enhanced Transistor Performance

Abstract

<P>GEOMETRICAL SCALING OF CMOS TRANSISTORS INTO THE NANOSCALE REGIME FOR IMPROVEMENTS IN DEVICE PERFORMANCE AND INTEGRATED CIRCUIT DENSITY HAS MET IMMENSE CHALLENGES. TECHNOLOGICAL BARRIERS RELATED TO THE LIMITATIONS OF MATERIAL PROPERTIES AND PROCESS TECHNOLOGIES GENERALLY IMPEDE THE PROGRESS FOR FURTHER PERFORMANCE IMPROVEMENT. ALTERNATIVE APPROACHES TO ADDRESS THESE CHALLENGES HAVE TO BE PURSUED IN ORDER TO REALIZE THE FULL POTENTIAL OF CMOS DEVICES. FUNDAMENTAL CHANGES TO THE DEVICE STRUCTURES AND MATERIALS USED IN A CONVENTIONAL MOSFET COUPLED WITH THE ADOPTION OF NOVEL PROCESS TECHNOLOGIES ARE DEEMED TO HOLD GREAT PROMISES FOR THE EVOLUTION OF FUTURE CMOS TECHNOLOGIES. ENHANCING THE CARRIER TRANSPORT IN THE SILICON (SI) CHANNEL IS ONE SUCH PROMISING SOLUTION TO FURTHER EXTEND THE TRANSISTOR PERFORMANCE IN ADDITION TO DEVICE SCALING. CARRIER MOBILITY IN SILICON CAN BE ENHANCED BY STRAIN-INDUCED MODIFICATION OF THE ELECTRONIC BAND STRUCTURE. THROUGH THE INTRODUCTION OF APPROPRIATE