Please use this identifier to cite or link to this item: https://doi.org/10.1109/TNANO.2015.2456510
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dc.titleHigh-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions
dc.contributor.authorKwon, Kon-Woo
dc.contributor.authorFong, Xuanyao
dc.contributor.authorWijesinghe, Parami
dc.contributor.authorPanda, Priyadarshini
dc.contributor.authorRoy, Kaushik
dc.date.accessioned2019-07-03T03:24:51Z
dc.date.available2019-07-03T03:24:51Z
dc.date.issued2015-11-01
dc.identifier.citationKwon, Kon-Woo, Fong, Xuanyao, Wijesinghe, Parami, Panda, Priyadarshini, Roy, Kaushik (2015-11-01). High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions. IEEE TRANSACTIONS ON NANOTECHNOLOGY 14 (6) : 1024-1034. ScholarBank@NUS Repository. https://doi.org/10.1109/TNANO.2015.2456510
dc.identifier.issn1536-125X
dc.identifier.issn1941-0085
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/156178
dc.description.abstract© 2002-2012 IEEE. In spin-transfer torque magnetic random access memory (STT-MRAM), retention-, write-, and read-failures negatively impact the memory yield and density. In this paper, we jointly consider device-circuit-architecture layers to implement high-density STT-MRAM array while meeting the target yield requirement. Different types of magnetic tunnel junctions are considered at the device level, and error correcting codes (ECCs) in conjunction with invert-coding are employed as an architectural solution. Through cross-layer interactions, we present a design methodology to optimize bit-cell area while satisfying the target yield and energy consumption under process variation. Furthermore, we explore the use of invert-coding along with ECC in order to achieve higher memory density than that obtained using ECC alone. Our proposed technique can improve memory density further by proper selection of thermal stability factor based upon two observations: 1) invert-coding can fix multiple write/read failures with small storage overhead and 2) as thermal stability factor increases, retention-failure probability exponentially decreases, and thus, simple ECC is good enough for retention failure correction.
dc.language.isoen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.sourceElements
dc.subjectScience & Technology
dc.subjectTechnology
dc.subjectPhysical Sciences
dc.subjectEngineering, Electrical & Electronic
dc.subjectNanoscience & Nanotechnology
dc.subjectMaterials Science, Multidisciplinary
dc.subjectPhysics, Applied
dc.subjectEngineering
dc.subjectScience & Technology - Other Topics
dc.subjectMaterials Science
dc.subjectPhysics
dc.subjectCache
dc.subjectdensity
dc.subjecterror correcting code
dc.subjectinvert coding
dc.subjectmagnetic tunnel junction (MTJ)
dc.subjectprocess variation
dc.subjectspin transfer torque magnetic random access memory (STT-MRAM)
dc.subjectthermal stability factor
dc.subjectyield
dc.subjectSPIN TRANSFER
dc.subjectANISOTROPY
dc.subjectMAGNETORESISTANCE
dc.subjectINPLANE
dc.subjectCACHE
dc.subjectPOWER
dc.subjectRAM
dc.typeArticle
dc.date.updated2019-07-03T03:05:05Z
dc.contributor.departmentDEPT OF ELECTRICAL & COMPUTER ENGG
dc.description.doi10.1109/TNANO.2015.2456510
dc.description.sourcetitleIEEE TRANSACTIONS ON NANOTECHNOLOGY
dc.description.volume14
dc.description.issue6
dc.description.page1024-1034
dc.published.statePublished
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