Please use this identifier to cite or link to this item:
https://doi.org/10.1109/TNANO.2015.2456510
DC Field | Value | |
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dc.title | High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions | |
dc.contributor.author | Kwon, Kon-Woo | |
dc.contributor.author | Fong, Xuanyao | |
dc.contributor.author | Wijesinghe, Parami | |
dc.contributor.author | Panda, Priyadarshini | |
dc.contributor.author | Roy, Kaushik | |
dc.date.accessioned | 2019-07-03T03:24:51Z | |
dc.date.available | 2019-07-03T03:24:51Z | |
dc.date.issued | 2015-11-01 | |
dc.identifier.citation | Kwon, Kon-Woo, Fong, Xuanyao, Wijesinghe, Parami, Panda, Priyadarshini, Roy, Kaushik (2015-11-01). High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions. IEEE TRANSACTIONS ON NANOTECHNOLOGY 14 (6) : 1024-1034. ScholarBank@NUS Repository. https://doi.org/10.1109/TNANO.2015.2456510 | |
dc.identifier.issn | 1536-125X | |
dc.identifier.issn | 1941-0085 | |
dc.identifier.uri | https://scholarbank.nus.edu.sg/handle/10635/156178 | |
dc.description.abstract | © 2002-2012 IEEE. In spin-transfer torque magnetic random access memory (STT-MRAM), retention-, write-, and read-failures negatively impact the memory yield and density. In this paper, we jointly consider device-circuit-architecture layers to implement high-density STT-MRAM array while meeting the target yield requirement. Different types of magnetic tunnel junctions are considered at the device level, and error correcting codes (ECCs) in conjunction with invert-coding are employed as an architectural solution. Through cross-layer interactions, we present a design methodology to optimize bit-cell area while satisfying the target yield and energy consumption under process variation. Furthermore, we explore the use of invert-coding along with ECC in order to achieve higher memory density than that obtained using ECC alone. Our proposed technique can improve memory density further by proper selection of thermal stability factor based upon two observations: 1) invert-coding can fix multiple write/read failures with small storage overhead and 2) as thermal stability factor increases, retention-failure probability exponentially decreases, and thus, simple ECC is good enough for retention failure correction. | |
dc.language.iso | en | |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |
dc.source | Elements | |
dc.subject | Science & Technology | |
dc.subject | Technology | |
dc.subject | Physical Sciences | |
dc.subject | Engineering, Electrical & Electronic | |
dc.subject | Nanoscience & Nanotechnology | |
dc.subject | Materials Science, Multidisciplinary | |
dc.subject | Physics, Applied | |
dc.subject | Engineering | |
dc.subject | Science & Technology - Other Topics | |
dc.subject | Materials Science | |
dc.subject | Physics | |
dc.subject | Cache | |
dc.subject | density | |
dc.subject | error correcting code | |
dc.subject | invert coding | |
dc.subject | magnetic tunnel junction (MTJ) | |
dc.subject | process variation | |
dc.subject | spin transfer torque magnetic random access memory (STT-MRAM) | |
dc.subject | thermal stability factor | |
dc.subject | yield | |
dc.subject | SPIN TRANSFER | |
dc.subject | ANISOTROPY | |
dc.subject | MAGNETORESISTANCE | |
dc.subject | INPLANE | |
dc.subject | CACHE | |
dc.subject | POWER | |
dc.subject | RAM | |
dc.type | Article | |
dc.date.updated | 2019-07-03T03:05:05Z | |
dc.contributor.department | ELECTRICAL AND COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/TNANO.2015.2456510 | |
dc.description.sourcetitle | IEEE TRANSACTIONS ON NANOTECHNOLOGY | |
dc.description.volume | 14 | |
dc.description.issue | 6 | |
dc.description.page | 1024-1034 | |
dc.published.state | Published | |
Appears in Collections: | Staff Publications Elements |
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Kwon et al. - 2015 - High-Density and Robust STT-MRAM Array Through Device | 1.1 MB | Adobe PDF | OPEN | Published | View/Download |
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