Please use this identifier to cite or link to this item: https://doi.org/10.1109/JETCAS.2016.2547701
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dc.titleHigh Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM
dc.contributor.authorSeo, Yeongkyo
dc.contributor.authorKwon, Kon-Woo
dc.contributor.authorFong, Xuanyao
dc.contributor.authorRoy, Kaushik
dc.date.accessioned2019-07-03T03:23:47Z
dc.date.available2019-07-03T03:23:47Z
dc.date.issued2016-09-01
dc.identifier.citationSeo, Yeongkyo, Kwon, Kon-Woo, Fong, Xuanyao, Roy, Kaushik (2016-09-01). High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM. IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 6 (3) : 293-304. ScholarBank@NUS Repository. https://doi.org/10.1109/JETCAS.2016.2547701
dc.identifier.issn2156-3357
dc.identifier.issn2156-3365
dc.identifier.urihttps://scholarbank.nus.edu.sg/handle/10635/156177
dc.description.abstract© 2011 IEEE. This paper proposes a dual (1R/1W) port spin-orbit torque magnetic random access memory (1R/1W SOT-MRAM) for energy efficient on-chip cache applications. Our proposed dual port memory can alleviate the impact of write latency on system performance by supporting simultaneous read and write accesses. The spin-orbit device leverages the high spin current injection efficiency of spin Hall metal to achieve low critical switching current to program a magnetic tunnel junction. The low write current reduces the write power consumption, and the size of the access transistors, leading to higher integration density. Furthermore, the decoupled read and write current paths of the spin-orbit device improves oxide barrier reliability, because the write current does not flow through the oxide barrier. Device, circuit, and system level co-simulations show that a 1R/1W SOT-MRAM based L2 cache can improve the performance and energy-efficiency of the computing systems compared to SRAM and standard STT-MRAM based L2 caches.
dc.language.isoen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.sourceElements
dc.subjectScience & Technology
dc.subjectTechnology
dc.subjectEngineering, Electrical & Electronic
dc.subjectEngineering
dc.subjectDual 1R/W port
dc.subjecton-chip memory
dc.subjectspin hall metal (SHM)
dc.subjectspin-orbit torque (SOT)
dc.subjectspin-transfer torque magnetic random access memory (STT-MRAM)
dc.subjectSTT-MRAMS
dc.subjectFUTURE
dc.subjectARCHITECTURE
dc.subjectINPLANE
dc.typeArticle
dc.date.updated2019-07-03T03:03:45Z
dc.contributor.departmentDEPT OF ELECTRICAL & COMPUTER ENGG
dc.description.doi10.1109/JETCAS.2016.2547701
dc.description.sourcetitleIEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
dc.description.volume6
dc.description.issue3
dc.description.page293-304
dc.published.statePublished
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