KEY FACTORS STUDY OF HIGH Q INDUCTOR FABRICATED BY CMOS TECHNOLOGY

Abstract

A new demand for interconnect architectures is the inclusion of on-chip passive elements. This includes high quality factor (Q) inductors for realizing advanced RF applications. Integration of inductor on silicon chips is faced with challenges from Cu/low-k (dielectric constant) unit processes that have to meet inductor design specifications. This project aimed to study the key factors especially stresses that affect the fabrication of high Q inductor, while overall fabrication process development of inductor microstructures in the top layer of interconnect was still in concern. Stress evaluation included the influence of dielectric film thickness and insertion layers on residual stress and thermal stress. It was found that the residual stress increased as the dielectric film thickness increased. The inserted BLOk layer successfully avoided the dielectric film fracture. A model of stress components was proposed to explain the stress dependency. The inductor was fabricated using advanced Cu/Low-k single damascene Back End of Line technology at the Institute of Microelectronics. Fabrication processes such as dielectric deposition, trench etching, electroplating and chemical mechanical polishing for high Q inductor have been developed. In-line process control showed challenges in etching and electroplating processes. Preliminary process development of the on-chip inductor was successful but full optimization and integration is needed.