FABRICATION AND CHARACTERIZATION OF SOI MOSFETS

Abstract

The purpose of this project is to understand the fabrication and electrical characterization of silicon-on-insulator (SOI) metal-on-semiconductor field-effect transistors (MOSFETs). An array of SOI n-channel MOSFETs (nMOSFETs) with different channel lengths and silicon (Si) body thickness has been fabricated and is being analyzed for electrical characteristics. We concentrated on fabricating fully depleted (FD) SOI MOSFETs and partially depleted (PD) SOI MOSFETs, and based our electrical properties analysis on the data obtained from them. The FD and PD devices are obtained by using different ion implantation conditions. Major process challenges include (a) Photo resist (PR) trimming process and (b) Silicidation processes on thin Si device layer. To analyze the electrical properties of different nMOSFETs, electrical measurement of the threshold voltage (VTH), output characteristics (ID-VD), transconductance (gm) and subthreshold slope was performed on the devices. For SOI MOSFETs, especially n-channel partially depleted SOI MOSFETs, the kink effect exists in the output characteristics (ID-VD). The kink effect can be explained by the increased body potential caused by holes generated by impact ionization near the drain.