A TARGET WIP MODEL FOR SEMICONDUCTOR PRODUCTION PLANNING

Abstract

Semiconductor manufacturing is one of the most capital-intensive and complex manufacturing processes. The short product life cycle and fast changing market demand makes production planning important for the semiconductor production. Considerable research efforts have been made in the last three decades to solve the production planning problem in semiconductor manufacturing. In this thesis, we describe a target WIP model for the semiconductor production planning. Three objectives are extracted from the production requirement: (1) meet the material output demand and maximize the material output according to priority, (2) adjust the sitting WIP level to the ideal sitting WIP level in order to achieve the objective process Cycle Time (CT), (3) balance the workload on critical scanners in order to reduce the risk from the variability in the manufacturing line. The challenge for this model comes from the uncertainty in CT. CT is affected by sitting WIP levels, machine loading level and process time. To overcome this problem, we describe a decomposition of CT and introduce a concept of Basic Cycle Time (BCT). We can solve the problem of CT uncertainty by using BCT and sitting WIP adjustment. Because of the complexity of manufacturing process, the production planning model is a large scale model. In this thesis, we demonstrate how to implement this model by reducing the problem size and improving the solving speed for this large scale model. We first test our model on a small scale data to show the functionality of our model and then test our model on the real line data to show the solving speed. The large scale model with 40,000 variables and 48,000 constraints can be solved within 5 minutes using ILog OPL. Results show that the production plan produced by our model is able to meet the objectives.