SIMULATION & DESIGN OF LANGE COUPLER FOR CMOS FABRICATION PROCESS

Abstract

Characterization of the transmission line on 0.18 micron CMOS technology was done in the form of a Lange coupler design on multiple metal layers. This work is motivated by the use of the SiO2 dielectric as the separating layer between the conducting lines and the ground plane, as opposed to the traditional use of the substrate. This allows the use of low resistivity silicon substrate, yet achieving the performance of high-resistivity gallium arsenide. Basic characterization involves the study of the matching impedances. Coupling effects are also studied with variations in the line widths and spacing. The basic design technique involves the analysis of the even- and odd-mode impedances and using established identities to relate this information to the geometries of the Lange coupler. These identities involve, firstly, the consideration of a single transmission line. The corresponding dimensions are found and scaled to the two-folded-lines for the Lange coupler. A correction term is added to account for the thickness of the conductor. It is found that the spaces between the lines scale with the impedance and line widths scale inversely. These results, together with the coupling, are drawn on a plot for the variation of impedance. This, then, can be used as an approximate tool for the design of other Lange couplers with different load impedances. A sample design was made and initial simulations with HP Momentum show good results. Fabrication was done that included the use of Cadence tools for drawing the layout.